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1 ltc1278 s f ea t u re d u escriptio the ltc ? 1278 is a 1.6 m s, 500ksps, sampling 12-bit a/d converter that draws only 75mw from a single 5v or 5v supplies. this easy-to-use device comes complete with a 200ns sample-and-hold, a precision reference and an internally trimmed clock. unipolar and bipolar conver- sion modes add to the flexibility of the adc. the low power dissipation is made even more attractive by a 8.5mw power-down feature. instant wake-up from shut- down allows the converter to be powered down even during brief inactive periods. the ltc1278 converts 0v to 5v unipolar inputs from a single 5v supply and 2.5v bipolar inputs from 5v supplies. maximum dc specs include 1lsb inl and 1lsb dnl. outstanding guaranteed ac performance includes 70db s/(n + d) and 78db thd at the input frequency of 100khz over temperature. the internal clock is trimmed for 1.6 m s conversion time. the clock automatically synchronizes to each sample command, eliminating problems with asynchronous clock noise found in competitive devices. a separate convert start input and a data ready signal (busy) ease connec- tions to fifos, dsps and microprocessors. n single supply 5v or 5v operation n two speed grades,500ksps (LTC1278-5) 400ksps (ltc1278-4) n 70db s/(n + d) and 74db thd at nyquist n no missing codes over temperature n 75mw (typ) power dissipation n power shutdown with instant wake-up n internal reference can be overdriven externally n internal synchronized clock; no clock required n high impedance analog input n 0v to 5v or 2.5v input range n new flexible, friendly parallel interface to dsps and fifos n 24-pin narrow pdip and sw packages 12-bit, 500ksps sampling a/d converter with shutdown u a o pp l ic at i ty p i ca l effective bits and signal-to-(noise + distortion) vs input frequency input frequency (hz) 10k 0 effective number of bits s/(n + d) (db) 3 5 7 10 100k 1m 2m lt1278 g4 1 4 6 9 12 11 62 56 74 68 8 2 f sample = 500khz nyquist frequency u s a o pp l ic at i n high speed data acquisition n digital signal processing n multiplexed data acquisition systems n audio and telecom processing n spectrum analysis , ltc and lt are registered trademarks of linear technology corporation. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a in v ref agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd v ss busy cs rd convst shdn dv dd d0 d1 d2 d3 LTC1278-5 + 0.1 m f 10 m f 2.42v reference output analog input (0v to 5v) 10 m f 0.1 m f 5v 12-bit parallel bus m p control lines ltc1278 ?ta01 + conversion start input power down input single 5v supply, 500khz, 12-bit sampling a/d converter
2 ltc1278 a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number av dd = dv dd = v dd (notes 1, 2) supply voltage (v dd ) .............................................. 12v negative supply voltage (v ss ) bipolar operation only .......................... C 6v to gnd total supply voltage (v dd to v ss ) bipolar operation only ....................................... 12v analog input voltage (note 3) unipolar operation ................... C 0.3v to v dd + 0.3v bipolar operation............... v ss C 0.3v to v dd + 0.3v digital input voltage (note 4) unipolar operation ................................ C 0.3v to 12v bipolar operation........................... v ss C 0.3v to 12v digital output voltage unipolar operation ................... C 0.3v to v dd + 0.3v bipolar operation................ v ss C 0.3v to v dd + 0.3v power dissipation ............................................. 500mw operating temperature range ltc1278-4c, LTC1278-5c ..................... 0 c to 70 c ltc1278-4i ....................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c 1 2 3 4 5 6 7 8 9 10 11 12 top view sw package 24-lead plastic so wide n package 24-lead pdip 24 23 22 21 20 19 18 17 16 15 14 13 a in v ref agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd v ss busy cs rd convst shdn dv dd d0 d1 d2 d3 t jmax = 110 c, q ja = 100 c/w (n) t jmax = 110 c, q ja = 130 c/w (sw) consult factory for military grade parts. ltc1278-4cn LTC1278-5cn ltc1278-4in ltc1278-4csw LTC1278-5csw ltc1278-4isw ltc1278-4/LTC1278-5 parameter conditions min typ max units resolution (no missing codes) l 12 bit integral linearity error (note 7) l 1 lsb differential linearity error l 1 lsb offset error (note 8) 4 lsb l 6 lsb gain error 15 lsb gain error tempco i out(ref) = 0 l 10 45 ppm/ c cc hara terist ics co u verter with internal reference (notes 5, 6) ltc1278-4/LTC1278-5 symbol parameter conditions min typ max units v in analog input range (note 9) 4.95v v dd 5.25v (unipolar) l 0 to 5 v 4.75v v dd 5.25v, C 5.25v v ss C 2.45v (bipolar) l 2.5 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions (sample mode) 45 pf during conversions (hold mode) 5 pf put u i a a u log (note 5)
3 ltc1278 symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 100khz input signal l 70 72 db 250khz input signal 70 db thd total harmonic distortion 100khz input signal l C80 C78 db first 5 harmonics 250khz input signal C 74 db peak harmonic or spurious noise 100khz input signal l C84 C78 db 250khz input signal C 74 db imd intermodulation distortion f in1 = 99.37khz, f in2 = 102.4khz C 82 db f in1 = 249.37khz, f in2 = 252.4khz C 70 db full power bandwidth 4 mhz full linear bandwidth (s/(n + d) 3 68db) 350 khz (note 5) ltc1278-4/LTC1278-5 accuracy ic dy u w a parameter conditions min typ max units v ref output voltage i out = 0 2.400 2.420 2.440 v v ref output tempco i out = 0 l 10 45 ppm/ c v ref line regulation 4.95v v dd 5.25v 0.01 lsb/v C 5.25v v ss C 4.95v 0.01 lsb/v v ref load regulation 0v | i out | 1ma 2 lsb/ma ltc1278-4/LTC1278-5 i ter al refere ce characteristics u uu (note 5) symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.95v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.95v i o = C 10 m a 4.7 v i o = C 200 m a l 4v v ol low level output voltage v dd = 4.95v i o = 160 m a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz high z output leakage d11 to d0 v out = 0v to v dd , cs high l 10 m a c oz high z output capacitance d11 to d0 cs high (note 9 ) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma ltc1278-4/LTC1278-5 (note 5) digital i puts a d digital outputs u u
4 ltc1278 symbol parameter conditions min typ max units v dd positive supply voltage (notes 10, 11) unipolar 4.95 5.25 v bipolar 4.75 5.25 v v ss negative supply voltage (note 10) bipolar only C 2.45 C 5.25 v i dd positive supply current f sample = 500ksps l 15.0 29.5 ma shdn = 0v l 1.7 3.0 ma i ss negative supply current f sample = 500ksps, v ss = C 5v l 0.12 0.30 ma p d power dissipation f sample = 500ksps l 75.0 150 mw shdn = 0v l 8.5 15 mw (note 5) power require e ts w u ltc1278-4/LTC1278-5 symbol parameter conditions min typ max units f sample(max) maximum sampling frequency ltc1278-4 l 400 khz LTC1278-5 l 500 t sample(min) minimum throughput time ltc1278-4 l 2.5 m s (acquisition time plus conversion time) LTC1278-5 l 2.0 m s t conv conversion time ltc1278-4 2.0 2.3 m s LTC1278-5 1.6 1.85 m s t acq acquisition time 200 ns t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 20 ns t 3 shdn - to convst wake-up time (note 10) 350 ns t 4 convst low time (notes 10, 12) l 40 ns t 5 convst to busy delay c l = 100pf 40 110 ns commercial l 130 ns industrial l 140 ns t 6 data ready before busy - c l = 100pf l 20 40 ns t 7 wait time rd after busy - mode 2, (see figure 14) (note 9) l C20 ns t 8 data access time after rd c l = 20pf (note 9) 50 90 ns commercial l 110 ns industrial l 120 ns c l = 100pf 70 125 ns commercial l 150 ns industrial l 170 ns t 9 bus relinquish time 20 30 75 ns commercial l 20 85 ns industrial l 20 90 ns t 10 rd low time (note 9) l t 8 ns t 11 convst high time (notes 9, 12) l 40 ns t 12 aperture delay of sample-and-hold jitter < 50ps 15 ns ltc1278-4/LTC1278-5 (note 5) ti i g characteristics w u
5 ltc1278 note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 1/2lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: a in must not exceed v dd or fall below v ss by more than 50mv for specified accuracy. therefore the minimum supply voltage for the unipolar mode is 4.95v. the minimum for the bipolar mode is 4.75v, C 2.45v. note 12: the falling convst edge starts a conversion. if convst returns high at a bit decision point during the conversion it can create small errors. for best performance ensure that convst returns high either within 120ns after conversion start (i.e., before the first bit decision) or after busy rises (i.e., after the last bit test). see mode 1a and 1b (figures 12 and 13) timing diagrams. ti i g characteristics w u the l indicates specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss (ground for unipolar mode) or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 60ma below v ss (ground for unipolar mode) or above v dd without latch-up. note 4: when these pin voltages are taken below v ss (ground for unipolar mode), they will be clamped by internal diodes. this product can handle input currents greater than 60ma below v ss (ground for unipolar mode) without latch-up. these pins are not clamped to v dd . note 5: av dd = dv dd = v dd = 5v, (v ss = C 5v for bipolar mode), f sample = 400khz (ltc1278-4), 500khz (LTC1278-5), t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for unipolar and bipolar modes. (note 5) typical perfor m a n ce characteristics u w integral nonlinearity vs output code code 0 ?.0 inl error (lsb) 0.5 0 0.5 1.0 512 1024 1536 2048 lt1278 g1 2560 3072 3584 4096 f sample = 500khz code 0 ?.0 dnl error (lsb) 0.5 0 0.5 1.0 512 1024 1536 2048 lt1278 g2 2560 3072 3584 4096 f sample = 500khz differential nonlinearity vs output code input frequency (hz) 10k 0 effective number of bits s/(n + d) (db) 3 5 7 10 100k 1m 2m lt1278 g4 1 4 6 9 12 11 62 56 74 68 8 2 f sample = 500khz nyquist frequency enobs and s/(n + d) vs input frequency
6 ltc1278 input frequency (hz) 10k 100 amplitude (db below the fundamental) ?0 ?0 ?0 ?0 100k 2m 1m lt1278 g6 ?0 ?0 ?0 ?0 ?0 0 f sample = 500khz 3rd harmonic thd 2nd harmonic typical perfor m a n ce characteristics u w spurious free dynamic range vs input frequency input frequency (hz) 20 signal/(noise + distortion) (db) 40 50 70 80 1k 100k 1m 10m ltc1278 g10 0 10k 60 30 10 v in = 0db v in = 20db v in = 60db f sample = 500khz s/(n + d) vs input frequency and amplitude distortion vs input frequency input frequency (hz) 20 signal to noise ratio (db) 40 50 70 80 1k 100k 1m 10m ltc1278 g5 0 10k 60 30 10 f sample = 500khz signal-to-noise ratio (without harmonics) vs input frequency input frequency (hz) 10k ?00 spurious free dynamic range (db) ?0 ?0 ?0 ?0 100k 1m 2m ltltc1278 g11 ?0 ?0 ?0 ?0 ?0 0 f sample = 500khz frequency (hz) 0 ?20 amplitude (db) ?00 ?0 ?0 ?0 ?0 0 50k 100k 150k 200k ltc1278 g8 250k f sample = 500khz f in1 = 96.80khz f in2 = 101.68khz intermodulation distortion plot r source ( w ) 10 2500 acquisition time (ns) 3000 3500 4000 4500 100 1k 10k ltc1278 g9 2000 1500 500 0 1000 acquisition time vs source impedance load current (ma) ? 2.405 reference voltage (v) 2.410 2.415 2.420 2.425 2.430 2.435 4 ? ? 2 ltc1278 g12 ? 0 1 reference voltage vs load current ripple frequency (hz) 1k ?20 amplitude of power supply feedthrough (db) ?0 ?0 0 10k 100k 1m ltc1278 g7 ?0 ?0 ?00 f sample = 500khz av dd (v ripple = 1mv) dgnd (v ripple = 0.1v) v ss (v ripple = 10mv) power supply feedthrough vs ripple frequency temperature (c? ?5 0 supply current (ma) 5 10 15 20 ?5 0 25 50 ltc1278 g3 75 100 125 f sample = 500khz supply current vs temperature
7 ltc1278 rd (pin 20): read input. this enables the output drivers when cs is low. cs (pin 21): the chip select input must be low for the adc to recognize convst and rd inputs. busy (pin 22): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 23): negative supply. C 5v for bipolar opera- tion. bypass to agnd with 0.1 m f ceramic. analog ground for unipolar operation. av dd (pin 24): positive supply, 5v. bypass to agnd (10 m f tantalum in parallel with 0.1 m f ceramic). a in (pin 1): analog input. 0v to 5v (unipolar), 2.5v (bipolar). v ref (pin 2): 2.42v reference output. bypass to agnd (10 m f tantalum in parallel with 0.1 m f ceramic). agnd (pin 3): analog ground. d11 to d4 (pins 11 to 4): three-state data outputs. d11 is the most significant bit. dgnd (pin 12): digital ground. d3 to d0 (pins 13 to 16): three-state data outputs. dv dd (pin 17 ): digital power supply, 5v. tie to av dd pin. shdn (pin 18): power shutdown. convst (pin 19): conversion start signal. this active low signal starts a conversion on its falling edge (to recognize convst, cs has to be low). pi fu ctio s uu u 12-bit capacitive dac comparator 2.42v ref v ref c sample successive approximation register output latches ? ? d11 d0 busy control logic cs convst rd shdn internal clock zeroing switch dv dd v ss av dd (0v for unipolar mode or 5v for bipolar mode) a in agnd dgnd 12 12 ltc1278 ?bd fu ctio al block diagra uu w
8 ltc1278 conversion details the ltc1278 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of conversion the successive approxi- mation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during conversion, the internal 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in input connects to the sample-and-hold capacitor during the acquire phase, and the comparator test circuits load circuits for output float delay load circuits for access timing 3k c l dbn dgnd a) high-z to v oh (t 8 ) and v ol to v oh (t 6 ) c l dbn 3k 5v b) high-z to v ol (t 8 ) and v oh to v ol (t 6 ) dgnd ltc1278 ta08 3k 10pf dbn dgnd a) v oh to high-z 10pf dbn 3k 5v b) v ol to high-z dgnd 1278 ?ta08 shdn to convst wake-up timing t 3 shdn convst ltc1278 ?tc03 applicatio n s i n for m atio n wu u u offset is nulled by the feedback switch. in this acquire phase, a minimum delay of 200ns will provide enough time for the sample-and-hold capacitor to acquire the analog signal. during the convert phase, the comparator feedback switch opens, putting the comparator into the v dac ltc1278 f1 + c dac dac sample hold c sample s a r 12-bit latch comparator sample si a in figure 1. a in input cs to rd setup timing t 1 cs rd ltc1278 ?tc01 cs to convst setup timing t 2 cs convst ltc1278 ?tc02 ti i g diagra s wu w
9 ltc1278 compare mode. the input switch switches c sample to ground, injecting the analog input charge onto the sum- ming junction. this input charge is successively com- pared with the binary-weighted charges supplied by the capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the dac output balances the a in input charge. the sar contents (a 12-bit data word) which represent the a in are loaded into the 12-bit output latches. dynamic performance the ltc1278 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distor- tion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be exam- ined for frequencies outside the fundamental. figure 2 shows a typical ltc1278 fft plot. a 500khz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to the nyquist limit of 250khz. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 500khz the ltc1278 maintains very good enobs up to the nyquist input frequency of 250khz. refer to figure 3. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2 shows a typical spectral content with total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ? v 2 2 + v 3 2 + v 4 2 ... + v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd versus input input frequency (hz) 10k 0 effective number of bits s/(n + d) (db) 3 5 7 10 100k 1m 2m lt1278 g4 1 4 6 9 12 11 62 56 74 68 8 2 f sample = 500khz nyquist frequency figure 3. effective bits and signal-to-noise + distortion vs input frequency figure 2. ltc1278 nonaveraged, 4096 point fft plot applicatio n s i n for m atio n wu u u frequency (hz) 0 120 amplitude (db) 100 ?0 ?0 ?0 ?0 0 50k 100k 150k 200k ltc1278 f2 250k f sample = 500khz 5v f in = 97.045khz
10 ltc1278 applicatio n s i n for m atio n wu u u frequency is shown in figure 4. the ltc1278 has good distortion performance up to the nyquist frequency and beyond. figure 4. distortion vs input frequency intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb) and (fa C fb) while the 3rd order imd terms include (2fa + fb), (2fa C fb), (fa + 2fb), and (fa C 2fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd (fa ?fb) = 20log amplitude at (fa ?fb) amplitude at fa figure 5 shows the imd performance at a 100khz input. frequency (hz) 0 ?20 amplitude (db) ?00 ?0 ?0 ?0 ?0 0 50k 100k 150k 200k ltc1278 g8 250k f sample = 500khz f in1 = 96.80khz f in2 = 101.68khz peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full power and full linear bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1278 has been designed to optimize input bandwidth, allowing adc to undersample input signals with frequen- cies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) be- comes dominated by distortion at frequencies far beyond nyquist. driving the analog input the analog input of the ltc1278 is easy to drive. it draws only one small current spike while charging the sample- and-hold capacitor at the end of conversion. during con- version the analog input draws no current. the only requirement is that the amplifier driving the analog input must settle after the small current spike before the next figure 5. intermodulation distortion plot input frequency (hz) 10k 100 amplitude (db below the fundamental) ?0 ?0 ?0 ?0 100k 2m 1m lt1278 g6 ?0 ?0 ?0 ?0 ?0 0 f sample = 500khz 3rd harmonic thd 2nd harmonic
11 ltc1278 u s a o pp l ic at i wu u i for atio input voltage (v) 0v output code ? lsb ltc1278 ?f8b 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 fs = 5v 1lsb = fs/4096 figure 7. supplying a 2.5v reference voltage to the ltc1278 with the lt1019a-2.5 figure 8a. ltc1278 unipolar transfer characteristics conversion starts. any op amp that settles in 200ns to small current transients will allow maximum speed opera- tion. if slower op amps are used, more settling time can be provided by increasing the time between conversions. suitable devices capable of driving the adcs a in input include the lt1360, lt1220, lt1223 and lt1224 op amps. internal reference the ltc1278 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.42v. it is internally connected to the dac and is available at pin 2 to provide up to 1ma current to an external load. for minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10 m f tantalum in parallel with a 0.1 m f ceramic). the v ref pin can be driven with a dac or other means to provide input span adjustment in bipolar mode. the v ref pin must be driven to at least 2.45v to prevent conflict with the internal reference. the reference should be driven to no more than 4.8v to keep the input span within the 5v supplies. figure 6 shows an lt1006 op amp driving the reference pin. (in the unipolar mode, the input span is already 0v to 5v with the internal reference so driving the reference is not recommended, since the input span will exceed the supply and codes will be lost at the full scale.) figure 7 shows a typical reference, the lt1019a-2.5 connected to the ltc1278. this will provide an improved drift (equal to the maximum 5ppm/ c of the lt1019a-2.5) and a 2.582v full scale. figure 6. driving the v ref with the lt1006 op amp input voltage (v) 0v output code fs ?1lsb ltc1278 f8a 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs 4096 5v 4096 = unipolar/bipolar operation and adjustment figure 8a shows the ideal input/output characteristics for the ltc1278. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, ... fs C 1.5lsb). the output code is naturally binary with 1lsb = fs/4096 = 5v/4096 = 1.22mv. figure 8b shows the input/output transfer characteristics for the bipolar mode in twos complement format. figure 8b. ltc1278 bipolar transfer characteristics v ref(out) 3 2.45v 3 w input range 1.033v ref(out) 5v ?v + lt1006 ltc1278 a in agnd v ref 10 m f ltc1278 f6 3 w input range 2.58v (= 1.033 v ref ) ltc1278 a in agnd v ref 10 m f ltc1278 f7 lt1019a-2.5 v in gnd v out 5v 5v ?v
12 ltc1278 u s a o pp l ic at i wu u i for atio figure 9a. full-scale adjust circuit ltc1278 a in agnd ltc1278 f9a r4 100 w full-scale adjust r3 10k r2 10k r1 50 w v1 + a1 additional pins omitted for clarity 20lsb trim range unipolar offset and full-scale error adjustments in applications where absolute accuracy is important, then offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 9a shows the extra components required for full-scale error adjustment. if both offset and full-scale adjustments are needed, the circuit in figure 9b can be used. for zero offset error apply 0.61mv (i.e., 1/2lsb) at the input and adjust the offset trim until the ltc1278 output code flickers between 0000 0000 0000 and 0000 0000 0001. for zero full-scale error apply an analog input of 4.99817v (i.e., fs C 1 1/2lsb or last code transition) at the input and adjust r5 until the ltc1278 output code flickers between 1111 1111 1110 and 1111 1111 1111. bipolar offset and full-scale error adjustments bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. again, bipolar offset must be adjusted before full-scale error. bipolar offset error ad- justment is achieved by trimming the offset of the op amp driving the analog input of the ltc1278 while the input voltage is 1/2lsb below ground. this is done by applying an input voltage of C 0.61mv (C 0.5lsb) to the input in figure 9c and adjusting the r8 until the adc output code flickers between 0000 0000 0000 and 1111 1111 1111. for full-scale adjustment, an input voltage of 2.49817v (fs C 1.5lsbs) is applied to the input and r5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1278, a printed circuit board is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. high quality tantalum and ceramic bypass capacitors should be used at the av dd and v ref pins as shown in figure 10. for the bipolar mode, a 0.1 m f ceramic provides adequate bypassing for the v ss pin. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. input signal leads to a in and signal return leads from agnd (pin 3) should be kept as short as possible to minimize input noise coupling. in applications where this is not possible, a shielded cable between source and adc is recommended. figure 9c. ltc1278 bipolar offset and full-scale adjust circuit figure 9b. ltc1278 unipolar offset and full-scale adjust circuit a in ltc1278 f9b r2 10k r4 100k r1 10k 10k 5v r9 20 w analog input 0v to 5v r3 100k 5v r8 10k offset adjust r6 400 w r5 4.3k full-scale adjust r7 100k + ltc1278 a in ltc1278 f9c r2 10k r4 100k r1 10k analog input r3 100k 5v r8 20k offset adjust r6 200 w r5 4.3k full-scale adjust r7 100k + ltc1278 ?v
13 ltc1278 digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfac- ing. a separate convst is used to initiate a conversion. internal clock the a/d converter has an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 1.6 m s. no external adjustments are required, and with the typical acquisition time of 250ns, throughput performance of 500ksps is assured. power shutdown the ltc1278 provides a shutdown feature that will save power when the adc is in inactive periods. to power down the adc, pin 18 (shdn) needs to be driven low. when in power shutdown mode, the ltc1278 will not start a conversion even though the convst goes low. all the u s a o pp l ic at i wu u i for atio also, since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. a single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 3 (agnd) or as close as possible to the adc. pin 12 (dgnd) and all other analog grounds should be connected to this single analog ground point. no other digital grounds should be connected to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continu- ously active microprocessor bus, it is possible to get errors in conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be elimi- nated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to iso- late the adc data bus. figure 11. internal logic for control inputs cs, rd, convst and shdn figure 10. power supply grounding practice ltc1278 f10 a in agnd v ref av dd dv dd dgnd ltc1278 digital system 0.1 m f + analog ground plane ground connection to digital circuitry analog input circuitry 3 2 24 17 12 1 0.1 m f 10 m f 10 m f conversion start (rising edge trigger) ltc1278 f11 busy flip flop clear q d active high enable three-state outputs db11....db0 cs rd convst shdn
14 ltc1278 in mode 2 (figure 14) cs is tied low. the falling convst signal again starts the conversion. data outputs are in three-state until read by mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. in slow memory and rom modes (figures 15 and 16) cs is tied low and convst and rd are tied together. the mpu starts conversion and read the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor takes rd (= convst) low and starts the conversion. busy goes low forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results appear on the data outputs; busy goes high releasing the processor, and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low which starts a conversion and reads the previous conversion result. after the conversion is complete, the processor can read the new result (which will initiate another conversion). power is off except the internal reference which is still active and provides 2.42v output voltage to the other circuitry. in this mode the adc draws 8.5mw instead of 75mw (for minimum power, the logic inputs must be within 600mv of the supply rails). the wake-up time from the power shutdown to active state is 350ns. timing and control conversion start and data read operations are controlled by three digital inputs: cs, convst and rd. figure 11 shows the logic structure associated with these inputs. a logic 0 for convst will start a conversion after the adc has been selected (i.e., cs is low). once initiated it cannot be restarted until the conversion is complete. converter status is indicated by the busy output, and this is low while conversion is in progress. figures 12 through 16 show several different modes of operation. in modes 1a and 1b (figures 12 and 13) cs and rd are both tied low. the falling convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow low going convst pulse. mode 1b shows high going convst pulse. u s a o pp l ic at i wu u i for atio data (n-1) db11 to db0 convst busy ltc1278 f13 t conv t 5 t 11 t 6 cs = rd = 0 data n db11 to db0 data (n + 1) db11 to db0 data t 5 sample n sample n + 1 figure 13. mode 1b. convst starts a conversion. data outputs always enabled. (convst = ) sample n data (n-1) db11 to db0 cs = rd = 0 convst busy ltc1278 f12 t 4 t conv t 5 t 6 data n db11 to db0 data (n + 1) db11 to db0 data sample n + 1 figure 12. mode 1a. convst starts a conversion. data ouputs always enabled. (convst = )
15 ltc1278 u s a o pp l ic at i wu u i for atio figure 14. mode 2. convst starts a conversion. data is read by rd figure 15. slow memory mode figure 16. rom mode timing rd = convst busy ltc1278 f15 cs = 0 t conv t 5 data (n ?1) db11 to db0 data data n db11 to db0 data (n + 1) db11-db0 data n db11 to db0 t 9 t 8 t 6 sample n sample n + 1 rd = convst busy ltc1278 f16 cs = 0 t conv t 5 data (n ?1) db11 to db0 data data n db11 to db0 t 8 t 9 sample n sample n + 1 convst busy ltc1278 f14 t 4 t conv cs = 0 t 11 t 5 t 7 t 10 data n db11 to db0 data (n + 1) db11 to db0 t 9 t 8 rd data sample n sample n + 1 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 ltc1278 ? linear technology corporation 1994 1278fa lt/gp 0998 rev a 2k ? printed in usa u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. n package 24-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) part number description comments ltc1274/ltc1277 12-bit, 10mw, 100ksps a/d converters with 1 m a shutdown complete with clock reference ltc1279 12-bit, 600ksps sampling a/d converter with shutdown 70db sinad at nyquist, low power ltc1400 12-bit, 400ksps serial a/d converter complete high speed 12-bit adc in so-8 ltc1409 12-bit, 800ksps sampling a/d converter with shutdown fast, complete low power adc ltc1415 12-bit, 1.25msps sampling a/d converter with shutdown single 5v supply, low power: 55mw ltc1419 14-bit, 800ksps sampling a/d converter with shutdown 81.5db sinad, low power: 150mw related parts sw package 24-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s24 (wide) 0996 note 1 0.598 ?0.614* (15.190 ?15.600) 22 21 20 19 18 17 16 15 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 13 14 11 12 23 24 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com n24 1197 0.255 0.015* (6.477 0.381) 1.265* (32.131) max 12 3 4 5 6 7 8910 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)

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